1 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com november 2000, rev. 1 eco #13417 EDI2DL32256V description the EDI2DL32256Vxxbc is a 3.3v, 256kx32 synchronous pipeline burst sram constructed with two 256kx16 die mounted on a multi-layer laminate substrate. the device is packaged in a 119 lead, 14mm by 22mm, bga. it is available with clock speeds of166, 150 and 133 mhz. the device is a pipeline burst sram, allowing the user to develop a fast external memory for texas instruments ?6x? in burst mode data from the first memory location is available in three clock cycles, while the subsequent data is available in one clock cycle (3/1/1/1). subsequent burst ad- dresses are generated by the tms320c6x dsp. individual address locations can also be read, allowing one memory access in 3 clock cycles. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous in- puts include all addresses, all data inputs, chip enable (ce\), burst control input (adsc\), byte write enables (bw0\ to bw3\) and write enable (bwe\). asynchronous inputs include the output enable (oe\), burst mode control (mode), and sleep mode control (zz). the data outputs (dq), enabled by oe\, are also asynchronous. address lines and the chip enable are registered with the address status controller (adsc\) input pin. 256kx32 synchronous pipline burst sram 3.3v features t khqv times of 3.5, 3.8 and 4.0ns 166, 150 and 133 mhz clock speed dsp memory solution texas instruments?tms320c6201 texas instruments?tms320c67x package: 119 pin bga, jedec mo-163 3.3v operating supply voltage 3.5ns output enable access time single write control and output enable lines single chip enable line 56% space savings vs. monolithic tqfps multiple vcc and vss pins reduced inductance and capacitance block diagram fig. 1 123 4567 a v dd aanca av dd a b nc nc a adsc\ a a nc b c nc a a v dd aanc c d dq 16 nc v ss nc v ss nc dq 8 d e dq 18 dq 17 v ss ce\ v ss dq 9 dq 10 e f v dd dq 19 v ss oe\ v ss dq 11 v dd f g dq 21 dq 20 be 2 \ncbe 1 \dq 12 dq 13 g h dq 23 dq 22 v ss nc v ss dq 14 dq 15 h j v dd v dd nc v dd nc v dd v dd j k dq 31 dq 30 v ss clk v ss dq 6 dq 7 k l dq 29 dq 28 be 3 \ncbe 0 \dq 4 dq 5 l m v dd dq 27 v ss bwe\ v ss dq 3 v dd m n dq 26 dq 25 v ss a 1 v ss dq 1 dq 2 n p dq 24 nc v ss a 0 v ss nc dq 0 p r nc a mode v dd nc a nc r t nc nc a a a nc zz t u v dd nc nc nc nc nc v dd u 1 2345 67 pin configuration a 0 - 17 clk adsc\ oe\ bwe\ ce\ mode zz be 0 \ be 1 \ be 2 \ be 3 \ 256k x 16 ssram 256k x 16 ssram dq 0 - 7 dq 8 - 15 dq 16 - 23 dq 24 - 31
2 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com november 2000, rev. 1 eco #13417 EDI2DL32256V pin descriptions pin symbol type d escription various a 0-17 input addresses: these inputs are registered and must meet setup and hold times around the rising edge synchronous of clk. l5,g5 be0\,be1\, input byte write: a byte write is low for a write cycle and high for a read be2\, be3\ cycle. be0\ controls g3,l3 be2\,be3\ synchronous dq0-7. be1\ controls dq8-15. be2\ controls dq16-23. be3\ controls dq24-31 m4 bwe\ input byte write enable: this active low input gates byte write operations and must meet the setup and hold synchronous times around the rising edge of clk. k4 clk input clock:this signal registers the addresses, data, chip enables, write control and burst control inputs on synchronous its rising edge. all synchronous inputs must meet setup and hold times around the clock?s rising edge. e4 ce\ input chip enable: this active low inputs is used to enable the device. synchronous f4 oe\ input output enable: this active low asynchronous input enables the data output drivers b4 adsc\ input address status controller: this active low input causes device to be deselected or selected along with new synchronous external address to be registered. a read or write cycle is initiated depending upon write control inputs. r3 mode input static mode: this input selects the burst sequence. a low on this pin selects linear burst. a nc or high on this pin selects interleaved burst. t7 zz input snooze: this active high input puts the device in low power consumption standby mode. for normal synchronous operation, this input has to be either low or nc (no connect) various dq 0-31 input/output data inputs/outputs: first byte is dq 0-7 , second byte is dq 8-15 , third byte is dq 16-23 , fourth byte is dq 24-31 various vcc supply core power supply: +3.3v -5%/+5% various vss ground ground operation address used ce\ adsc\ write\ oe\ dq deselected cycle, power down none h l x x high-z write cycle, begin burst external l l l x d read cycle, begin burst external l l h l q read cycle, begin burst external l l h h high-z read cycle, suspend burst current x h h l q read cycle, suspend burst current x h h h high-z read cycle, suspend burst current h h h l q read cycle, suspend burst current h h h h high-z write cycle, suspend burst current x h l x d write cycle, suspend burst current h h l x d note: 1. x means ?don?t care?, h means logic high. l means logic low. 2a.write\ = l, means [be0\*be1\*be2\*be3\]*bwe\ equals low 2b.write\ = h, means [be0\*be1\*be2\*be3\]*bwe\ equals high 3. all inputs except oe\ must meet setup and hold times around the rising edge (low to high) of clk. 4. suspending burst generates wait cycle 5. for a write operation following a read operation, oe\ must be high before the input data required setup time plus high-z time for oe\ and staying high though out the input data hold time. 6. this device contains circuitry that will ensure the outputs will be in high-z during power-up. truth table
3 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com november 2000, rev. 1 eco #13417 EDI2DL32256V recommended operating conditions description symbol min max unit input high voltage v ih 2 vcc+0.3 v input low voltage v il -0.3 0.7 v supply voltage vcc 3.135 3.465 v capacitance (f = 1mhz, v in = v cc or v ss ) voltage on vcc supply relative to vss -0.5v to 4.6v v in -0.5v to vcc+0.5v storage temperature -55 c to +110 c junction temperature +110 c power dissipation 3 watts short circuit output current (per i/o) 20 ma * stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol max unit address lines c a tbd pf data lines c d/q tbd pf control lines c c tbd pf absolute maximum ratings* dc electrical characteristics (f = 1mhz, v in = v cc or vss) parameter symbol conditions min max units power supply current: operating i cc1 device selected; all inputs v il or v ih ; 850 ma cycle time t kc min; v cc = max; outputs open device deselected; v cc = max; all inputs cmos standby i sb2 v ss +0.2 or v cc -0.2; all inputs static; 20 ma clk frequency = 0 ttl standby i sb3 device deselected; all inputs v il or v ih ; 40 ma all inputs static; v cc = max; clk frequency = 0 ttl standby i sb4 device deselected; all inputs v il or v ih ; 40 ma v cc = max; clk cycle time t ck min input leakage current il i 0v < v in < v cc -2 2 a output leakage current il o output(s) disabled, 0v v out v cc -2 2 a output high voltage v oh i oh = -2.0ma 2.4 v output low voltage v ol i ol = 2.0ma 0.7 v ac test circuit ac test conditions 50 ? vt = 1.5v output z0 = 50 ? z0 = 50 ? parameter i/o unit input pulse levels v ss to 2.5 v input rise and fall times (max) 1.8 ns input and output timing levels 1.25 v output load see figure, at left ac output load equivalent 1.25v partial truth table function bwe\ be0\ be1\ be2\ be\3 read h x x x x write one byte (dq 0-7 )llhhh write all bytes l l l l l
4 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com november 2000, rev. 1 eco #13417 EDI2DL32256V ac electrical characteristics symbol 3.5ns 3.8ns 4.0ns description min max min max min max units clock clock cycle time t khkh 6 6.7 7.5 clock high time t khkl 2.4 2.6 2.8 clock low time t klkh 2.4 2.6 2.8 output times clock to output valid t khqv 3.5 3.8 4.0 clock to output in low-z t khqx 000 clock to output in high-z t khqz 1.5 6 1.5 6.7 1.5 7.5 oe to output valid t oelqv 3.5 3.5 3.8 oe to output in low-z t oelqx 000 oe to output in high-z t oehqz 3.5 3.5 3.8 setup times address status controller valid to clock t scvkh 1.5 1.5 1.5 address valid to clock t avkh 1.5 1.5 1.5 chip enable valid to clock t evkh 1.5 1.5 1.5 write enable (bwe\) valid to clock t wlkh 1.5 1.5 1.5 data valid to clock t dvkh 1.5 1.5 1.5 hold times address status controller hold time t khscx 0.5 0.5 0.5 address hold time t khax 0.5 0.5 0.5 chip enable hold time t khex 0.5 0.5 0.5 write enable (bwe\) hold time t khwx 0.5 0.5 0.5 data hold time t khdx 0.5 0.5 0.5
5 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com november 2000, rev. 1 eco #13417 EDI2DL32256V fig. 2 read timing clk write\ t khk l t kl k h t khk h ce\ t khex adsc\ t evkh t sc vk h t khscx dq t khq z t khq x q(a1) q(a2) q(a3) q(a4) t khq v q(a5) a5 addr t avkh t khax a1 a2 a3 a4 oe\ t oelq v t oelq x t oehqz
6 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com november 2000, rev. 1 eco #13417 fig. 3 write timing t khk l t kl k h t khk h t khg wx t t khdx t dvkh d ( a1) d ( a2 ) d ( a3 ) d ( a4 ) d ( a5 ) t evkh t sc vkh t khscx t khex t avkh t khax a1 a2 a3 a4 a5 wvkh khwx clk write\ ce\ adsc\ dq addr oe\ EDI2DL32256V
7 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com november 2000, rev. 1 eco #13417 EDI2DL32256V package description: 119 lead bga jedec mo-163 commercial temperature range (0 c to +70 c) part number t kq (ns) clock frequency package (mhz) no. EDI2DL32256V35bc 3.5 166 tbd EDI2DL32256V38bc 3.8 150 tbd EDI2DL32256V40bc 4.0 133 tbd ordering information all dimensions are in inches industrial temperature range (-40 c to +85 c) part number t kq (ns) clock frequency package (mhz) no. EDI2DL32256V40bi 4.0 133 tbd 0.110 max 0.028 max 0.050 typ 0.050 typ a b c d e f g h j k l m n p r t u 0.551 bsc pin 1 index 0.800 bsc 0.866 bsc 0.300 bsc r 0.062 max (4x)
8 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com november 2000, rev. 1 eco #13417 EDI2DL32256V fig. 5 interfacing the texas instruments tms320c6201 with the EDI2DL32256V (256kx32 ssram) notes: 1. either ce 0 or ce 2 can be used to enable the device. 2. when the zz pin is asserted high, the device will be in cmos standby mode regardless of the state of any other pins. while in standby mode the device will take one complete clock cycle to become active again after a low is asserted on the zz pin. one possible option for the designe r concerned about power is to tie the zz signal to the chip enable they are using for the device. any time the chip is disabled (by driving the chip enabl e pin high) the device will go into standby mode. standby mode can also be achieved by tying the zz pin low or allowing it to float and meeting all the signal cond itions specified in the data sheet. 3. use clkout1 for running the memory at the same clock speed as the c6x. use clkout2 for running the sbsram at one half the clo ck rate of the c6x. 4. the mode pin can be tied to vss (linear burst), tied to vcc (interleaved burst) or allowed to float (interleaved burst). ce\ zz be 3 \ be 2 \ be 1 \ be 0 \ oe\ adsc\ adv\ gw\ clk mode nc, vss, vcc ea 0-22 ed 0-31 a 0-17 dq 0-31 texas instruments tms320c6201 EDI2DL32256V (note 1) (note 2) (note 3) ce 2 \ ce 1 \ ce 0 \ be 3 \ be 2 \ be 1 \ be 0 \ ssoe\ ssads\ ssadv\ sswe\ clkout1 clkout2 (note 4)
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